People Collaborating in Our Research

In 2013-2021, following Co-Researcher of Dr Bishwajeet Pandey in order to create a globally educational excellence without borders among the youth, research scholars, academicians by growing of knowledge, imparting values and ethics. So, they will create a successful career for themselves as well as make significant contributions for society.

  1. Aarushi Aggarwal, Intel, USA
    1. LVCMOS-Based Low-Power Thermal-Aware Energy-Proficient Vedic Multiplier Design on Different FPGAs. Advances in Intelligent Systems and Computing, 115–122. doi:10.1007/978-981-10-8533-8_12
    2. Stub Series Terminal Logic-Based Low-Power Thermal-Aware Vedic Multiplier Design on 40-nm FPGA. Advances in Intelligent Systems and Computing, 107–113. doi:10.1007/978-981-10-8533-8_11
  2. Abdelmajid Badri, Hassan II University of Casablanca, Casablanca, Morocco
    1. “Smart Hybrid SDN Approach for MPLS VPN Management and Adaptive Multipath Optimal Routing”, Wireless Personal Communications, Vol. 114, pp. 1107-1131, April 2020. https://link.springer.com/article/10.1007/s11277-020-07411-1
    2. “Novel Approach for Management of Automated IPv6 Network Simulation”, Wireless Personal Communications, Vol. 111, pp. 1487–1504, April 2020. https://link.springer.com/article/10.1007/s11277-019-06928-4
    3. "Behavior analysis of VoIP performances in next-generation networks." International Journal of Engineering & Technology 7, no. 3.15 (2018): 353-359.
  3. Abhishek Jain, Thapar University, India
    1. "Energy Efficient and High Performance FIR Filter Design on Spartan-6FPGA" 3C Tecnologia. Special Issue, May 2019, https://www.3ciencias.com/wp-content/uploads/2019/05/eem17052019_2-1-1.pdf
  4. Achal Agarwal, Ajay Kumar Garg Engineering College, India
    1. LVCMOS-Based Low-Power Thermal-Aware Energy-Proficient Vedic Multiplier Design on Different FPGAs. Advances in Intelligent Systems and Computing, 115–122. doi:10.1007/978-981-10-8533-8_12
    2. Stub Series Terminal Logic-Based Low-Power Thermal-Aware Vedic Multiplier Design on 40-nm FPGA. Advances in Intelligent Systems and Computing, 107–113. doi:10.1007/978-981-10-8533-8_11
  5. Aditi Goyal, Chitkara University, Chandigarh, India
    1. "Processor Specific Data Processing Device (DPD) Design for Energy Efficient Data Center." International Journal of Energy, Information and Communications 6, no. 3 (2015): 29-38.
  6. Aditi Moudgil, Chitkara University, Chandigarh, India
    1. "SSTL Based Energy Efficient ISCAS’99 Benchmark Circuit Design on FPGA." International Journal of Energy, Information and Communications 6, no. 3 (2015): 39-46.
    2. “GTL Based Internet of Things Enable Processor Specific RAM Design on 65nm FPGA”, IEEE 57th International Symposium ELMAR-2015. 28-30 September 2015, Zadar, Croatia: the oldest conference in Europe. https://ieeexplore.ieee.org/document/7334514
  7. Aisha Hassan Abdalla Hashim, International Islamic University Malaysia, Kuala Lumpur, Malaysia
    1. “Design and Evaluation of a Multihoming-Based Mobility Management Scheme to Support Inter Technology Handoff in PNEMO”, Wireless Personal Communications volume 114, pp. 133–1153, May 2020 https://link.springer.com/article/10.1007/s11277-020-07412-0
    2. “A Novel Artificial Intelligence Based Timing Synchronization Scheme for Smart Grid Applications” Wireless Personal Communications volume 114, pp. 1067–1084, April 2020, https://link.springer.com/article/10.1007/s11277-020-07408-w
  8. Akash Kumar, NUST, Islamabad, Pakistan
    1. "Simulation of HSTL I/O standard based energy efficient frame buffer for digital image processor." In 2014 International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE), pp. 16-20. IEEE, 2014.
  9. Alisha Nagpal, Chitkara University, Chandigarh, India
    1. Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array. Advances in Intelligent Systems and Computing, 151–161. doi:10.1007/978-981-10-8533-8_15 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_15
  10. Amit Kant Pandit, SMVDU, India
    1. “Leakage power consumption of address register interfacing with different families of FPGA”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8, Issue- 9S2, July 2019 https://www.ijitee.org/wp-content/uploads/papers/v8i9S2/I11080789S219.pdf
    2. "Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA", International Journal of Innovative Technology and Exploring Engineering, Volume-8 Issue-9S2, pp. 530-533, July 2019.
  11. Amit Yadav, Chitkara University, Chandigarh, India
  12. Amanpreet Sandhu, Chitkara University, Chandigarh, India
    1. "Frequency Scaling Based Low Power ORIYA UNICODE READER (OUR) Design ON 40nm and 28nm FPGA", International Journal of Recent Technology and Engineering (IJRTE), ISSN: 2277-3878, Volume-7, Issue-6S, March 2019
  13. Amanpreet Kaur, Chitkara University, Chandigarh, India
    1. "SSTL Based Energy Efficient ISCAS’99 Benchmark Circuit Design on FPGA." International Journal of Energy, Information and Communications 6, no. 3 (2015): 39-46.
    2. “Pseudo Open Drain IO Standard Based Energy Efficient Solar Charge Sensor Design on 20nm FPGA”, 11th IEEE International Conference on Power Electronics and Drive Systems (PEDS), Sydney, Australia, 9 – 12 June 2015. https://ieeexplore.ieee.org/document/7203530
    3. "LVTTL Based Energy Efficient Watermark Generator Design and Implementation on FPGA", IEEE International Conference on ICT Convergence (ICTC), 22-24 October 2014, Busan, Korea, https://ieeexplore.ieee.org/document/6983240
    4. "Frequency Scaling Based Low Power ORIYA UNICODE READER (OUR) Design ON 40nm and 28nm FPGA", International Journal of Recent Technology and Engineering (IJRTE), ISSN: 2277-3878, Volume-7, Issue-6S, March 2019
  14. Anirudh Khanna, Chitkara University, India
    1. “A Discussion about Upgrading the Quick Script Platform to Create Natural Language based IoT Systems”, 2nd International Conference on Recent Trends in Computer Science and Electronics (RTCSE), 02-03 January 2017, Kuala Lumpur, Malaysia http://rtcse.org/RTCSE_2017.pdf
    2. "Anatomy and utilities of an artificial intelligence conversational entity." In 2015 International Conference on Computational Intelligence and Communication Networks (CICN), pp. 594-597. IEEE, 2015.
  15. Anjan Kumar, GLA University Mathura, India
  16. Anu Singla, Chitkara University, Chandigarh, India
  17. Anupam Shukla, ABV-IIITM, Gwalior, India
  18. Apoorv Verma, Chitkara University, Chandigarh, India
  19. Atiqur Rahman, South Asian University, Bangladesh
  20. Ayoub Bahnasse, Hassan II University of Casablanca, Casablanca, Morocco
    1. “Smart Hybrid SDN Approach for MPLS VPN Management and Adaptive Multipath Optimal Routing”, Wireless Personal Communications, Vol. 114, pp. 1107-1131, April 2020. https://link.springer.com/article/10.1007/s11277-020-07411-1
    2. “Novel Approach for Management of Automated IPv6 Network Simulation”, Wireless Personal Communications, Vol. 111, pp. 1487–1504, April 2020. https://link.springer.com/article/10.1007/s11277-019-06928-4
    3. "Behavior analysis of VoIP performances in next-generation networks." International Journal of Engineering & Technology 7, no. 3.15 (2018): 353-359.
  21. Azeddine Khiat, Hassan II University of Casablanca, Casablanca, Morocco
    1. “Smart Hybrid SDN Approach for MPLS VPN Management and Adaptive Multipath Optimal Routing”, Wireless Personal Communications, Vol. 114, pp. 1107-1131, April 2020. https://link.springer.com/article/10.1007/s11277-020-07411-1
    2. “Novel Approach for Management of Automated IPv6 Network Simulation”, Wireless Personal Communications, Vol. 111, pp. 1487–1504, April 2020. https://link.springer.com/article/10.1007/s11277-019-06928-4
    3. "Behavior analysis of VoIP performances in next-generation networks." International Journal of Engineering & Technology 7, no. 3.15 (2018): 353-359.
  22. B K Sarkar, TIT, Bhopal, India
    1. "Performance Evaluation of Backoff Method--Effect of Backoff Factor on Exponential Backoff Algorithm." In 2013 5th International Conference and Computational Intelligence and Communication Networks, pp. 82-86. IEEE, 2013.
  23. Balaji K, C-DAC, Noida, India
  24. Bhagwan Das, Tun Hussein Onn University of Malaysia
    1. Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA. Advances in Intelligent Systems and Computing, 123–137. doi:10.1007/978-981-10-8533-8_13 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_13
    2. "Technologies for effective disaster management systems: a state of the art survey of current challenges and opportunities", 3C Tecnología, Special Issue, November 2019 https://www.3ciencias.com/articulos/articulo/technologies-effective-disaster-management-systems/
    3. “Development of New All-Optical Signal Regeneration Technique”, Wireless Personal Communications, 95 (2), pp. 523-537, 2017. https://link.springer.com/article/10.1007/s11277-016-3907-3
    4. “Leakage power reduction with various IO standards and dynamic voltage scaling in vedic multiplier onvirtex-6 FPGA”, (2016) Indian Journal of Science and Technology, 9 (25), art. no. 97157, 2016. https://indjst.org/articles/leakage-power-reduction-with-various-io-standards-and-dynamic-voltage-scaling-in-vedic-multiplier-on-virtex-6-fpga
    5. “A Discussion about Upgrading the Quick Script Platform to Create Natural Language based IoT Systems”, 2nd International Conference on Recent Trends in Computer Science and Electronics (RTCSE), 02-03 January 2017, Kuala Lumpur, Malaysia http://rtcse.org/RTCSE_2017.pdf
    6. “GTL Based Internet of Things Enable Processor Specific RAM Design on 65nm FPGA”, IEEE 57th International Symposium ELMAR-2015. 28-30 September 2015, Zadar, Croatia: the oldest conference in Europe. https://ieeexplore.ieee.org/document/7334514
    7. “Temperature Control of Pseudo Noise Generator Based Optical Transmitter using Airflow and Heat Sink Profile at High Speed Transceiver Logic IO Standard”, Int. Conf. on Sensors, Materials and Manufacturing (ICSMM), Ho-Chi-Minh, Vietnam, February 2015. http://www.joace.org/uploadfile/2015/0529/20150529042946338.pdf
  25. Bhale Pradeep Kumar, IIIT Gwalior, India
  26. Bhanu Sharma, Chitkara University, Chandigarh, India
  27. BS Chowdhry, Mehran University, Sind, Pakistan
    28. \
    1. “Prologue: Recent trends in computer science and engineering (RTCSE)”, 3C Tecnologia. Special Issue, April 2020 https://www.3ciencias.com/wp-content/uploads/2020/04/prologue_ee_3c-tecno_abril-2020-1.pdf
    2. "Energy Efficient and High Performance FIR Filter Design on Spartan-6FPGA" 3C Tecnologia. Special Issue, May 2019, https://www.3ciencias.com/wp-content/uploads/2019/05/eem17052019_2-1-1.pdf
    3. IoTs Enable Active Contour Modeling Based Energy Efficient and Thermal Aware Object Tracking on FPGA”, Wireless Personal Communications, 85 (2), pp. 529-543, 2015. https://link.springer.com/article/10.1007/s11277-015-2753-z
    4. "Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA", Wireless Personal Communications, Vol. 76, No. 3, 2014, pp 569-578. https://link.springer.com/article/10.1007/s11277-014-1725-z
    5. “Frequency, voltage and temperature sensor design for fire detection in VLSI circuit on FPGA”, Communications in Computer and Information Science, Vol. 414, 2013 pp. 121-133 https://link.springer.com/chapter/10.1007/978-3-319-10987-9_12
  28. Carlos La Rosa, Universidad Nacional Mayor de San Marcos, Lima, Peru
    1. "Deep Learning Applied to Capacity Control in Commercial Establishments in Times of COVID-19”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242584
  29. Chafloque, Renzo,Universidad Nacional Mayor de San Marcos, Lima, Peru
    1. "Deep Learning Audio Spectrograms Processing to the Early COVID-19 Detection”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242583
  30. Ciro Rodriguez Rodriguez, Facultad de Ingeniería de Sistemas, Universidad Nacional Mayor de San Marcos, Lima, Peru and Facultad de Ingeniería Informatica y Electronica, Universidad Nacional Federico Villarreal, Lima, Peru,
    1. "Deep Learning Applied to Capacity Control in Commercial Establishments in Times of COVID-19”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242584
    2. “Environment Friendly FSM Design on Ultrascale Architecture: An Energy Efficient Green Computing Approach”, World Journal of Engineering, 2020, https://www.emerald.com/insight/content/doi/10.1108/WJE-08-2020-0397/full/html
    3. “Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru”, World Journal of Engineering ISSN: 1708-5284 https://www.emerald.com/insight/content/doi/10.1108/WJE-09-2020-0416/full/html
    4. "Predictive Model for Safe Unconfinement Commercial Environments in Times of COVID-19", Solid State Technology, Vol. 63 No. 1s (2020) http://solidstatetechnology.us/index.php/JSST/article/view/3097
    5. “Prologue: Recent trends in computer science and engineering (RTCSE)”, 3C Tecnologia. Special Issue, April 2020 https://www.3ciencias.com/wp-content/uploads/2020/04/prologue_ee_3c-tecno_abril-2020-1.pdf
  31. Daizy Gupta, Gyancity Research Lab, Finland
  32. Daniel Angeles,Universidad Nacional Mayor de San Marcos, Lima, Peru
    1. "Deep Learning Audio Spectrograms Processing to the Early COVID-19 Detection”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242583
  33. Deepa Singh, ABV-IIITM Gwalior, India
    1. "Anatomy and utilities of an artificial intelligence conversational entity." In 2015 International Conference on Computational Intelligence and Communication Networks (CICN), pp. 594-597. IEEE, 2015.
    2. "Low Voltage Digitally Controlled Impedance Based Energy Efficient Vedic Multiplier Design on 28nm FPGA." In 2014 International Conference on Computational Intelligence and Communication Networks, pp. 951-955. IEEE, 2014.
    3. "Capacitance Based Low Power ALU Design and Implementation on 28nm FPGA." International Journal of Scientific Engineering and Technology 2, no. 6 (2013): 465-468.
    4. Pandey, Bishwajeet, Deepa Singh, Deepak Baghel, Jyotsana Yadav, and Manisha Pattanaik. "Clock Gated Low Power Memory Implementation on Virtex-6 FPGA." In 2013 5th International Conference and Computational Intelligence and Communication Networks, pp. 409-412. IEEE, 2013.
    5. "IO standard based low power design of RAM and implementation on FPGA." Journal of Automation and Control Engineering 1, no. 4 (2013).
    6. "IO standard based green multiplexer design and implementation on FPGA." In 2013 5th International Conference and Computational Intelligence and Communication Networks, pp. 428-431. IEEE, 2013.
    7. "Performance Evaluation of Backoff Method--Effect of Backoff Factor on Exponential Backoff Algorithm." In 2013 5th International Conference and Computational Intelligence and Communication Networks, pp. 82-86. IEEE, 2013.
  34. Deepak Baghel, MPCT, Gwalior, India
  35. Deepshikha Bhatt, Chitkara University, Chandigarh, India
  36. Devanshi Mahajan, Gyancity Research Lab, Finland
  37. Diana Luque, Universidad Nacional Mayor de San Marcos, Lima, Peru
    1. "Deep Learning Applied to Capacity Control in Commercial Establishments in Times of COVID-19”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242584
  38. Diksha Jain, Chitkara University, Chandigarh, India
  39. Dil Muhammad Akbar Hussain, Aalborg University Esbjerg, Esbjerg, Denmark,
    1. “Environment Friendly FSM Design on Ultrascale Architecture: An Energy Efficient Green Computing Approach”, World Journal of Engineering, 2020, https://www.emerald.com/insight/content/doi/10.1108/WJE-08-2020-0397/full/html
    2. “Energy Efficient Design on 16nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate”, Journal of Computational and Theoretical Nano Sciences
    3. FSM Based Green Memory Design and its Implementation on Ultrascale Plus FPGA”, Journal of Critical Reviews, ISSN- 2394-5125, Vol. 7, No. 19, pp.454-458, 2020 http://www.jcreview.com/fulltext/197-1594819368.pdf?1596969111
    4. "Energy Efficient and High Performance FIR Filter Design on Spartan-6FPGA" 3C Tecnologia. Special Issue, May 2019, https://www.3ciencias.com/wp-content/uploads/2019/05/eem17052019_2-1-1.pdf
    5. “Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA”, Wireless Personal Communications, 2019, Volume 106, No. 4, pp 1813–1826. https://link.springer.com/article/10.1007/s11277-018-5717-2
    6. “Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network”, Wireless Personal Communications, 2017, Vol.95, No. 2, pp 375–389. https://link.springer.com/article/10.1007/s11277-016-3898-0
    7. “Heuristic and Statistical Power Estimation Model for FPGA Based Wireless Systems”, Wireless Personal Communications, Vol. 106, pages. 2087–2098, 2019 https://link.springer.com/article/10.1007/s11277-018-5927-7
    8. “Different I/O Standard and Technology Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA”, Wireless Personal Communications, 2017,Volume 96,No.2,pp 3139–3158. https://link.springer.com/article/10.1007/s11277-017-4345-6
    9. “Environment Friendly FSM Design on Ultrascale Architecture: An Energy Efficient Green Computing Approach”, World Journal of Engineering, 2020, https://www.emerald.com/insight/content/doi/10.1108/WJE-08-2020-0397/full/html
    10. “Energy Efficient Design on 16nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate”, Journal of Computational and Theoretical Nano Sciences (Accepted)
    11. “FSM Based Green Memory Design and its Implementation on Ultrascale Plus FPGA”, Journal of Critical Reviews, ISSN- 2394-5125, Vol. 7, No. 19, pp.454-458, 2020 http://www.jcreview.com/fulltext/197-1594819368.pdf?1596969111
    12. “Leakage power consumption of address register interfacing with different families of FPGA”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8, Issue- 9S2, July 2019 https://www.ijitee.org/wp-content/uploads/papers/v8i9S2/I11080789S219.pdf
    13. “Scaling of supply voltage in design of energy saver FIR filter on 28nm FPGA”, International Journal of Control and Automation, 10 (12), pp. 77-88, 2017. http://article.nadiapub.com/IJCA/vol10_no12/7.pdf
    14. “Clock gating based energy efficient and thermal aware design for Vedic equation solver on 28nm and 40nmFPGA”, International Journal of Control and Automation, 9 (7), 2016, pp. 101-112. http://article.nadiapub.com/IJCA/vol9_no7/10.pdf
    15. “Leakage power reduction with various IO standards and dynamic voltage scaling in vedic multiplier onvirtex-6 FPGA”, (2016) Indian Journal of Science and Technology, 9 (25), art. no. 97157, 2016. https://indjst.org/articles/leakage-power-reduction-with-various-io-standards-and-dynamic-voltage-scaling-in-vedic-multiplier-on-virtex-6-fpga
    16. "Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA", International Journal of Innovative Technology and Exploring Engineering, Volume-8 Issue-9S2, pp. 530-533, July 2019. https://www.ijitee.org/wp-content/uploads/papers/v8i9S2/I11110789S219.pdf
    17. “Timing constraints-based high-performance DES design and implementation on 28-nm FPGA”, Advances in Intelligent Systems and Computing, 732, pp. 123-137, 2018. https://link.springer.com/chapter/10.1007/978-981-10-8533-8_13
    18. “A discussion about upgrading the quick script platform to create natural language based IoT systems”, Indian Journal of Science and Technology, 9 (46), art. no. 106917, 2016. https://indjst.org/articles/a-discussion-about-upgrading-the-quick-script-platform-to-create-natural-language-based-iot-systems
    19. “FPGA based low power DES algorithm design and implementation using HTML technology”, International Journal of Software Engineering and its Applications, 10 (6), pp. 81-92, 2016. https://www.scopus.com/sourceid/21100199850
    20. “HSTL IO standard based energy efficient multiplier design using Nikhilam navatashcaramam dashatah on 28nm FPGA”, International Journal of Control and Automation, 8 (8), 2015, pp. 35-44. http://article.nadiapub.com/IJCA/vol8_no8/5.pdf
    21. “Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA”, 5th International Conference on Green Computing and Engineering Technologies (ICGCET), 17-19 September 2019, Hotel Diwan, 31 Boulevard Hassan Seghir, Casablanca 20000, Morocco. http://icgcet.org/ICGCET_2019.pdf
    22. “Energy Efficient and High Performance FIR Filter Design on Spartan-6 FPGA”, 2nd International Multi-Topic Conference on Engineering and Science (IMCES'19), 05-07 May 2019, Holiday Inn Mauritius Mon Tresor , Mon Tresor, Plaine Magnien, Mauritius. http://imces.tech/IMCES_2019.pdf
    23. “Frequency Scaling and High Speed Transceiver Logic Based Low Power UART design on 45nm FPGA”, 11th International Conference on Computational Intelligence and Communication Networks (CICN), January 2019, Honolulu, HI, USA, https://ieeexplore.ieee.org/document/8902375
    24. "Role of Scaling of Frequency and Toggle Rate in POD IO Standards Based Energy Efficient ALU Design on Ultra Scale FPGA", 10th International Conference on Computational Intelligence and Communication Networks (CICN), Esbjerg, Denmark, 2018, pp. 50-53. https://ieeexplore.ieee.org/document/8864933
    25. “Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA”, 3rd International conference on Recent Trends in Computer Science and Electronics Engineering (RTCSE'18), 02-03 January 2018, Bangkok, Thailand http://www.rtcse.org/RTCSE_2018.pdf
    26. “Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling”, IEEE Saudi Arabia Smart Grid Conference (SASG 2017), 12th - 14th Dec, 2017, Jeddah Hilton Hotel, Jeddah, Saudi Arabia. https://ieeexplore.ieee.org/document/8356479
    27. “Stack Memory Implementation and Analysis of Timing Constraint, Power and Memory using FPGA”, IEEE 9th International Conference on Computational Intelligence and Communication Networks (CICN), 16-17 Sep 2017, Final International University, Cyprus. https://ieeexplore.ieee.org/document/8319388
    28. “A Discussion about Upgrading the Quick Script Platform to Create Natural Language based IoT Systems”, 2nd International Conference on Recent Trends in Computer Science and Electronics (RTCSE), 02-03 January 2017, Kuala Lumpur, Malaysia http://rtcse.org/RTCSE_2017.pdf
    29. “Power Analysis of Energy Efficient des Algorithm and Implementation on 28nm FPGA”, IEEE 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science (DCABES), 24-26 August 2016, Paris, France http://ieeexplore.ieee.org/document/7982309/
    30. “SSTL Based Thermal and Power Efficient RAM Design on 28nm FPGA for Spacecraft”, IEEE 2016 International Conference on Smart Grid and Clean Energy Technologies, 19-22 October 2016, University of Electronic Science and Technology of China (UESTC), Chengsu, China. http://ieeexplore.ieee.org/document/7876075/
    31. “GTL Based Internet of Things Enable Processor Specific RAM Design on 65nm FPGA”, IEEE 57th International Symposium ELMAR-2015. 28-30 September 2015, Zadar, Croatia: the oldest conference in Europe. https://ieeexplore.ieee.org/document/7334514
    32. “Pseudo Open Drain IO Standard Based Energy Efficient Solar Charge Sensor Design on 20nm FPGA”, 11th IEEE International Conference on Power Electronics and Drive Systems (PEDS), Sydney, Australia, 9 – 12 June 2015. https://ieeexplore.ieee.org/document/7203530
    33. "LVTTL Based Energy Efficient Watermark Generator Design and Implementation on FPGA", IEEE International Conference on ICT Convergence (ICTC), 22-24 October 2014, Busan, Korea, https://ieeexplore.ieee.org/document/6983240
    34. “Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA”, Scopus 4th International Conference on Advanced Materials and Engineering Materials (ICAMEM), 19-20 October 2014, Hong Kong. http://www.scientific.net/AMR.1082.467
    35. "IO Standard Based Thermal/Energy Efficient Green Communication For Wi-Fi Protected Access on FPGA", 6th IEEE International Congress on Ultra-Modern Telecommunications and Control systems and Workshops (ICUMT), St. Petersburg, Russia, 06-08 October 2014, https://ieeexplore.ieee.org/document/7002085
  40. Disha Chauhan, Chitkara University, Himachal Pradesh, India
  41. Divya Gaba, Chandigarh University, Chandigarh, India
  42. Diya Garg, Gyancity Research Lab, India
  43. Doris Esenarro Vargas, INERN Specialized Institute for Research on Ecosystems and Natural Resources, Universidad Nacional Federico Villarreal, Lima, Peru
    1. “Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru”, World Journal of Engineering ISSN: 1708-5284 https://www.emerald.com/insight/content/doi/10.1108/WJE-09-2020-0416/full/html
    2. "LVTTL and SSTL IO Standards Based Energy Efficient FSM Design on 16nm Ultrascale Plus FPGA”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242605
    3. "Deep Learning Applied to Capacity Control in Commercial Establishments in Times of COVID-19”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242584
    4. “Prologue of Special Issue on «6th International Conference on Green Computing and Engineering Technologies» Herzen State Pedagogical University of Russia, St Petersburg, Russia.”, 3C Tecnologia. Special Issue, November 2020 https://www.3ciencias.com/wp-content/uploads/2020/11/prologue-ed-esp-oct-2020-3c-tecno-1.pdf
  44. Fatima Ezzahraa Louhab, Hassan II University of Casablanca, Casablanca, Morocco
    1. “Smart Hybrid SDN Approach for MPLS VPN Management and Adaptive Multipath Optimal Routing”, Wireless Personal Communications, Vol. 114, pp. 1107-1131, April 2020. https://link.springer.com/article/10.1007/s11277-020-07411-1
    2. “Novel Approach for Management of Automated IPv6 Network Simulation”, Wireless Personal Communications, Vol. 111, pp. 1487–1504, April 2020. https://link.springer.com/article/10.1007/s11277-019-06928-4
    3. "Behavior analysis of VoIP performances in next-generation networks." International Journal of Engineering & Technology 7, no. 3.15 (2018): 353-359.
  45. Freddy Kaseng, Universidad Nacional Federico Villarreal, Lima, Peru
    1. "Predictive Model for Safe Unconfinement Commercial Environments in Times of COVID-19", Solid State Technology, Vol. 63 No. 1s (2020) http://solidstatetechnology.us/index.php/JSST/article/view/3097
    2. "Deep Learning Audio Spectrograms Processing to the Early COVID-19 Detection”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242583
  46. Frits Palomino Vera, Department of the Faculty of Forestry Research, Universidad Nacional Agraria de la Selva, Tingo Maria, Peru
    1. “Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru”, World Journal of Engineering ISSN: 1708-5284 https://www.emerald.com/insight/content/doi/10.1108/WJE-09-2020-0416/full/html
  47. Furqan Fazili, IUST, Awantipora, India
  48. Gaurav Verma, Jaypee Institute of Technology, India
  49. Geetam Singh Tomar, Department of ECE, Birla Institute of Applied Sciences, Bhimtal, India
    1. “Environment Friendly FSM Design on Ultrascale Architecture: An Energy Efficient Green Computing Approach”, World Journal of Engineering, 2020, https://www.emerald.com/insight/content/doi/10.1108/WJE-08-2020-0397/full/html
    2. “Energy Efficient Design on 16nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate”, Journal of Computational and Theoretical Nano Sciences
    3. FSM Based Green Memory Design and its Implementation on Ultrascale Plus FPGA”, Journal of Critical Reviews, ISSN- 2394-5125, Vol. 7, No. 19, pp.454-458, 2020 http://www.jcreview.com/fulltext/197-1594819368.pdf?1596969111
    4. “Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA”, Wireless Personal Communications, 2019, Volume 106, No. 4, pp 1813–1826. https://link.springer.com/article/10.1007/s11277-018-5717-2
    5. “Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network”, Wireless Personal Communications, 2017, Vol.95, No. 2, pp 375–389. https://link.springer.com/article/10.1007/s11277-016-3898-0
    6. "Performance Evaluation of Backoff Method--Effect of Backoff Factor on Exponential Backoff Algorithm." In 2013 5th International Conference and Computational Intelligence and Communication Networks, pp. 82-86. IEEE, 2013.
  50. Guiseppe A. Farulla, Italy Email: giuseppe.airof@gmail.com
    1. “Design and Review of Water Management System using Ethernet, Wi-Fi 802.11n, Modbus, and other communication standards”, Wireless Personal Communications, 2019, Volume 106, No. 4, pp 1677–1699. https://link.springer.com/article/10.1007/s11277-018-5380-7
  51. Gurpreet Singh, University of Lethbridge, Alberta, Canada
  52. Hasmatullah Noori, South Asian University, Afghanistan
  53. Harkinder Kaur, Chitkara University, Chandigarh, India
  54. Himanshu Verma, JIIT Noida, India
  55. Ipsita Singh, JIIT Noida, India
  56. Inderpreet Kaur, JIIT Noida, India
    1. Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array. Advances in Intelligent Systems and Computing, 151–161. doi:10.1007/978-981-10-8533-8_15 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_15
  57. Jagdish Kumar, National Knowledge Network Labs, India
  58. Jason Levy, Unviersity of Hawaii, USA
    1. Guest Editor of November 2019 Special Issue with Prof Jason Levy of University of Hawaii USA, Special Issue Website: https://www.3ciencias.com/revistas/revista/3c-tecnologia-ed-esp-noviembre-2019/
    2. Guest Editor of April 2020 Special Issue with Prof Jason Levy of University of Hawaii USA, Special Issue Website: https://www.3ciencias.com/revistas/revista/3c-tecnologia-edicion-especial-special-issue-abril-april-2020/
    3. "Technologies for effective disaster management systems: a state of the art survey of current challenges and opportunities", 3C Tecnología, Special Issue, November 2019 https://www.3ciencias.com/articulos/articulo/technologies-effective-disaster-management-systems/
    4. "Energy Efficient and High Performance FIR Filter Design on Spartan-6FPGA" 3C Tecnologia. Special Issue, May 2019 https://www.3ciencias.com/wp-content/uploads/2019/05/eem17052019_2-1-1.pdf
    5. “Prologue: Recent trends in computer science and engineering (RTCSE)”, 3C Tecnologia. Special Issue, April 2020 https://www.3ciencias.com/wp-content/uploads/2020/04/prologue_ee_3c-tecno_abril-2020-1.pdf
    6. “Combining the ethics and science of disaster management: key issues, policy considerations and best practices”, 3C Tecnología, Special Issue, November 2019 https://www.3ciencias.com/articulos/articulo/combining-ethics-science
    7. “Energy Efficient and High Performance FIR Filter Design on Spartan-6 FPGA”, 2nd International Multi-Topic Conference on Engineering and Science (IMCES'19), 05-07 May 2019, Holiday Inn Mauritius Mon Tresor , Mon Tresor, Plaine Magnien, Mauritius. http://imces.tech/IMCES_2019.pdf
  59. Jyotsana Yadav, Gwalior Engineering College, India
  60. K R Dayo, Mehran University, Sind, Pakistan
  61. Kanika Garg, Chitkara University, Chandigarh, India
    1. "SSTL Based Energy Efficient ISCAS’99 Benchmark Circuit Design on FPGA." International Journal of Energy, Information and Communications 6, no. 3 (2015): 39-46.
    2. “GTL Based Internet of Things Enable Processor Specific RAM Design on 65nm FPGA”, IEEE 57th International Symposium ELMAR-2015. 28-30 September 2015, Zadar, Croatia: the oldest conference in Europe. https://ieeexplore.ieee.org/document/7334514
  62. Karandeep Kaur, Accenture, India
  63. Kartik Kaliya, Gyancity Research Lab, India
  64. Kavita Goswami, Chitkara University, Chandigarh, India
    1. "Low Voltage Digitally Controlled Impedance Based Energy Efficient Vedic Multiplier Design on 28nm FPGA." In 2014 International Conference on Computational Intelligence and Communication Networks, pp. 951-955. IEEE, 2014.
  65. Keshav Kumar, Gyancity Research Lab, India
    1. “Leakage power consumption of address register interfacing with different families of FPGA”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8, Issue- 9S2, July 2019 https://www.ijitee.org/wp-content/uploads/papers/v8i9S2/I11080789S219.pdf
    2. "Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA", International Journal of Innovative Technology and Exploring Engineering, Volume-8 Issue-9S2, pp. 530-533, July 2019.
    3. "Frequency Scaling Based Low Power ORIYA UNICODE READER (OUR) Design ON 40nm and 28nm FPGA", International Journal of Recent Technology and Engineering (IJRTE), ISSN: 2277-3878, Volume-7, Issue-6S, March 2019
    4. Energy efficient instruction register for green communication. International Journal of Engineering and Advanced Technology. 8. 312-314.
    5. "Low Power UART Design Using Different Nanometer Technology Based FPGA." In 2018 8th International Conference on Communication Systems and Network Technologies (CSNT), pp. 1-3. IEEE, 2018.
    6. "Effect of Different Nano Meter Technology Based FPGA on Energy Efficient UART Design." In 2018 8th International Conference on Communication Systems and Network Technologies (CSNT), pp. 1-4. IEEE, 2018.
    7. "Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA." International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-8 Issue-12S2, October 2019
    8. "Power Efficient UART Design Using Capacitive Load on Different Nanometer Technology FPGA." Gyancity Journal of Engineering and Technology 5, no. 2 (2019).
  66. Khyati Nanda, HP, India
  67. Kulbhushan Sharma, Chitkara University, Himachal Pradesh, India
  68. Kumar Gaurav, South Asian University, India
  69. Kumar Satyam, Fast Conversion Lab, New Delhi, India
  70. Kumar Shashi Kant, Symbiosis Institute of Technology, India
  71. Kushagra Vashishta, Chitkara University, Chandigarh, India
  72. Lakshay Kalra, Chitkara University, Chandigarh, India
  73. Lakshay Rohilla, Chitkara University, Chandigarh, India
    1. Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array. Advances in Intelligent Systems and Computing, 151–161. doi:10.1007/978-981-10-8533-8_15 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_15
  74. Love Kumar, Bridge Network, India
  75. Ludovico Iovino, Italy Email:
    1. “Design and Review of Water Management System using Ethernet, Wi-Fi 802.11n, Modbus, and other communication standards”, Wireless Personal Communications, 2019, Volume 106, No. 4, pp 1677–1699. https://link.springer.com/article/10.1007/s11277-018-5380-7
  76. M. F. Alam, Indus University, Pakistan
  77. M.F.L Abdullah, Tun Hussein Onn University of Malaysia
    1. Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA. Advances in Intelligent Systems and Computing, 123–137. doi:10.1007/978-981-10-8533-8_13 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_13
  78. Madhu Maya Limbu, South Asian University, Bhutan
    1. "Simulation of HSTL I/O standard based energy efficient frame buffer for digital image processor." In 2014 International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE), pp. 16-20. IEEE, 2014.
  79. Madhavika Agarwal, GLA University Mathura, India
  80. Mahua Bhatacharya, ABV-IIITM Gwalior, India
  81. Manisha Pattanaik, ABV-IIITM Gwalior, India
  82. Manoj Bhatt, HCL Noida, India
  83. Mansee Jain, Chitkara University, Chandigarh, India
    1. "Anatomy and utilities of an artificial intelligence conversational entity." In 2015 International Conference on Computational Intelligence and Communication Networks (CICN), pp. 594-597. IEEE, 2015.
  84. Manvendra, South Asian University, India
  85. Marco Indaco, Italy Email:
    1. “Design and Review of Water Management System using Ethernet, Wi-Fi 802.11n, Modbus, and other communication standards”, Wireless Personal Communications, 2019, Volume 106, No. 4, pp 1677–1699. https://link.springer.com/article/10.1007/s11277-018-5380-7
  86. Mayank Kumar, EXL Technologies, India
  87. Md Hashim Minver, Addalaichenai National College Of Education, Srilanka
  88. Md. Mahbub-E-Noor, University of Barisal, Bangladesh
  89. Md Abdur Razzaque, Green University of Bangladesh, Dhaka, Bangladesh
    1. “Design and Evaluation of a Multihoming-Based Mobility Management Scheme to Support Inter Technology Handoff in PNEMO”, Wireless Personal Communications volume 114, pp. 133–1153, May 2020 https://link.springer.com/article/10.1007/s11277-020-07412-0
    2. “A Novel Artificial Intelligence Based Timing Synchronization Scheme for Smart Grid Applications” Wireless Personal Communications volume 114, pp. 1067–1084, April 2020, https://link.springer.com/article/10.1007/s11277-020-07408-w
  90. Meenakshi Bansal, Punjabi University, India
  91. Mohd Shah Nor Shahida, Tun Hussein Onn University of Malaysia
  92. Mohamed Talea, Hassan II University of Casablanca, Casablanca, Morocco
    1. “Smart Hybrid SDN Approach for MPLS VPN Management and Adaptive Multipath Optimal Routing”, Wireless Personal Communications, Vol. 114, pp. 1107-1131, April 2020. https://link.springer.com/article/10.1007/s11277-020-07411-1
    2. “Novel Approach for Management of Automated IPv6 Network Simulation”, Wireless Personal Communications, Vol. 111, pp. 1487–1504, April 2020. https://link.springer.com/article/10.1007/s11277-019-06928-4
    3. "Behavior analysis of VoIP performances in next-generation networks." International Journal of Engineering & Technology 7, no. 3.15 (2018): 353-359.
  93. Mohammad Kamrul Hasan, Universiti Kebangsaan Malaysia, Bangi, Malaysia
    1. “Design and Evaluation of a Multihoming-Based Mobility Management Scheme to Support Inter Technology Handoff in PNEMO”, Wireless Personal Communications volume 114, pp. 133–1153, May 2020 https://link.springer.com/article/10.1007/s11277-020-07412-0
    2. “A Novel Artificial Intelligence Based Timing Synchronization Scheme for Smart Grid Applications” Wireless Personal Communications volume 114, pp. 1067–1084, April 2020, https://link.springer.com/article/10.1007/s11277-020-07408-w
  94. Muse Mohamud Ahmed, Universiti Malaysia Sarawak, Kota Samarahan, Malaysia
    1. “A Novel Artificial Intelligence Based Timing Synchronization Scheme for Smart Grid Applications” Wireless Personal Communications volume 114, pp. 1067–1084, April 2020, https://link.springer.com/article/10.1007/s11277-020-07408-w
  95. Narpat Singh, RVS Group of Institutions, Coimbatore
  96. Navreet Kaur, Chitkara University, Chandigarh, India
  97. Navya Bhasin, Chitkara University, Chandigarh, India
  98. Neha Agrawal, GLA University Mathura, India
  99. Neha Bansal, Thapar University, Patiala, India
  100. Neha Tomar, South Asian University, India
  101. Neha Baishander, JIIT Noida, India
  102. Nirmal Roberts, ABV-IIITM Gwalior, India
  103. Nitish Rajoria, IIT Hyderabad, India
  104. Noor Zaman, King Faisal University, Saudi Arabia
  105. Othman Omran Khalifa, International Islamic University Malaysia, Kuala Lumpur, Malaysia
    1. “Design and Evaluation of a Multihoming-Based Mobility Management Scheme to Support Inter Technology Handoff in PNEMO”, Wireless Personal Communications volume 114, pp. 133–1153, May 2020 https://link.springer.com/article/10.1007/s11277-020-07412-0
  106. Om Jee Pandey, IIT Kanpur, India
  107. Pardeep Kumar, QUEST, Nawabshah, Pakistan
  108. Parkash Kumar, IIU, Islamabad, Pakistan
  109. Payal Tanwar, Chitkara University, Chandigarh, India
  110. Paolo Prinetto, Italy Email:
    1. “Design and Review of Water Management System using Ethernet, Wi-Fi 802.11n, Modbus, and other communication standards”, Wireless Personal Communications, 2019, Volume 106, No. 4, pp 1677–1699. https://link.springer.com/article/10.1007/s11277-018-5380-7
  111. Pervesh Kumar, Sungkyunkwan University, South Korea
    1. "Energy Efficient and High Performance FIR Filter Design on Spartan-6FPGA" 3C Tecnologia. Special Issue, May 2019, https://www.3ciencias.com/wp-content/uploads/2019/05/eem17052019_2-1-1.pdf
  112. Pooja Saigal, South Asian University, India
  113. Prabhat Ranjan Singh, South Asian University, India
  114. Pradip Swarnkar, ABV-IIITM Gwalior, India
  115. Preet Mohan Singh, Chitkara University, Chandigarh, India
  116. Puneet Tomar, Gyancity Research Lab, New Delhi, India
  117. Qadir Bakhsh, Tun Hussein Onn University of Malaysia
  118. Rahul Yadav, South Asian University, India
  119. Rajendra Aaseri, Lovely Professional University, India
  120. Rajina R. Mohamed, Universiti Tenaga Nasional, Kajang, Malaysia
  121. Rakesh Kumar, Chitkara University, Chandigarh, India
  122. Rashmi Sharma, Gyancity Research Lab, India
    1. Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA. Advances in Intelligent Systems and Computing, 139–150. doi:10.1007/978-981-10-8533-8_14 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_14
  123. Rashid Siddique Parhyar, COMSATS, Lahore, Pakistan
  124. Ravikant Kumar, University of Hyderabad, India
  125. Ravinder Kaur, Punjab University, India
  126. Ravneet Singh, Chitkara University, Chandigarh, India
  127. Rishita Saini, Chitkara University, Chandigarh, India
  128. Ritika Mahajan, Chitkara University, Chandigarh, India
  129. Robin Singh Bhadoria, Birla Institute of Applied Sciences, Bhimtal, India
    1. “Environment Friendly FSM Design on Ultrascale Architecture: An Energy Efficient Green Computing Approach”, World Journal of Engineering, 2020, https://www.emerald.com/insight/content/doi/10.1108/WJE-08-2020-0397/full/html
    2. “Prologue of Special Issue on «6th International Conference on Green Computing and Engineering Technologies» Herzen State Pedagogical University of Russia, St Petersburg, Russia.”, 3C Tecnologia. Special Issue, November 2020 https://www.3ciencias.com/wp-content/uploads/2020/11/prologue-ed-esp-oct-2020-3c-tecno-1.pdf
  130. Rohit Kumar, ABV-IIITM Gwalior, India
  131. Ronald H. Puerta,Department of the Faculty of Forestry Research, Universidad Nacional Agraria de la Selva, Tingo Maria, Peru
    1. “Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru”, World Journal of Engineering ISSN: 1708-5284 https://www.emerald.com/insight/content/doi/10.1108/WJE-09-2020-0416/full/html
  132. S J Bendra, South Asian University, Srilanka
  133. S.H.A. Musavi, Indus University, Pakistan
  134. Saifur Rahman, NSTU, Noakhali, Bangladesh.
  135. S.M.M. Islam, South Asian University, Bangladesh
  136. Sakshi Aggarwal, JIIT, Noida, India
  137. Samer Al-Madinah Bamansoor, International University, Shah Alam, Malaysia
  138. Saravjeet Singh, Chitkara University, Chandigarh, India
  139. Shabeer Ahmad, Gran Sasso Science Institute, L'Aquila, Italy
    1. "LVTTL and SSTL IO Standards Based Energy Efficient FSM Design on 16nm Ultrascale Plus FPGA”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242605
    2. “Leakage power consumption of address register interfacing with different families of FPGA”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8, Issue- 9S2, July 2019 https://www.ijitee.org/wp-content/uploads/papers/v8i9S2/I11080789S219.pdf
    3. "Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA", International Journal of Innovative Technology and Exploring Engineering, Volume-8 Issue-9S2, pp. 530-533, July 2019.
  140. Shaina Verma, Chandigarh Group of Colleges, Mohali, India
  141. Shalini Jain, IIIT Gwalior, India
  142. Shashank Jaiswal, South Asian University, India
  143. Sheifali Gupta, Chitkara University, Chandigarh, India
  144. Shikhar Maheshwari, JIIT, Noida
  145. Shiva Verma, Chitkara University, Chandigarh, India
  146. Shivani Madhok, HP, India
  147. Shivani Wadhwa, Chitkara University, Chandigarh, India
  148. Shivangni Singh, GLA University, Mathura, India
  149. Shriya Chauhan, Chitkara University, Chandigarh, India
  150. Shubham Gargrish, Gyancity Research Lab, India
  151. Shyala Islam, UCSI University, Kuala Lumpur, Malaysia
    1. “Design and Evaluation of a Multihoming-Based Mobility Management Scheme to Support Inter Technology Handoff in PNEMO”, Wireless Personal Communications volume 114, pp. 133–1153, May 2020 https://link.springer.com/article/10.1007/s11277-020-07412-0
    2. “A Novel Artificial Intelligence Based Timing Synchronization Scheme for Smart Grid Applications” Wireless Personal Communications volume 114, pp. 1067–1084, April 2020, https://link.springer.com/article/10.1007/s11277-020-07408-w
  152. Syarilla Iryani Ahmad Saany, Universiti Sultan Zainal Abidin, Kuala Terengganu, Malaysia
  153. Siddharth Saurabh, Giant Meterwave Radio Telescope, Khodad, Pune, India
    1. LVCMOS-Based Low-Power Thermal-Aware Energy-Proficient Vedic Multiplier Design on Different FPGAs. Advances in Intelligent Systems and Computing, 115–122. doi:10.1007/978-981-10-8533-8_12
    2. Stub Series Terminal Logic-Based Low-Power Thermal-Aware Vedic Multiplier Design on 40-nm FPGA. Advances in Intelligent Systems and Computing, 107–113. doi:10.1007/978-981-10-8533-8_11
    3. Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA. Advances in Intelligent Systems and Computing, 139–150. doi:10.1007/978-981-10-8533-8_14 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_14
  154. Simran Chhabra, Chitkara University, Chandigarh, India
  155. Simran Kaur Sindhu, Chitkara University, Chandigarh, India
    1. “SSTL based power efficient implementation of DES security algorithm on 28nm FPGA”, International Journal of Security and its Applications, 9 (7), 2015, pp. 267-274. http://article.nadiapub.com/IJSIA/vol9_no7/23.pdf
  156. SM Tanvir Siddiquee, Tsinghua University, China
  157. Sourabh Patel, ABV-IIITM Gwalior, India
  158. Sujeet Pandey, Jain University, Banglore, India
  159. Sujit Kumar Thakur, South Asian University, Nepal
  160. Sukhbani Kaur Virdi, JIIT Noida, India
  161. Sumit Banshal, South Asian University, Bangladesh
  162. Sumit Sharma, Chitkara University, Chandigarh, India
  163. Sumita Nagah, Gyancity Research Lab, India
  164. Sunny Singh, Chitkara University, Chandigarh, India
  165. SushantShekhar, JIIT Noida, India
  166. Suvriti,Thapar University, Patiala, India
  167. Sweety Dabbas, Maharaja Surajmal Institute, Janakpuri, Delhi, India
    1. LVCMOS-Based Low-Power Thermal-Aware Energy-Proficient Vedic Multiplier Design on Different FPGAs. Advances in Intelligent Systems and Computing, 115–122. doi:10.1007/978-981-10-8533-8_12
    2. Stub Series Terminal Logic-Based Low-Power Thermal-Aware Vedic Multiplier Design on 40-nm FPGA. Advances in Intelligent Systems and Computing, 107–113. doi:10.1007/978-981-10-8533-8_11
    3. Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA. Advances in Intelligent Systems and Computing, 139–150. doi:10.1007/978-981-10-8533-8_14 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_14
  168. Tamanna Walia, Chitkara University, Chandigarh, India
  169. Tanesh Kumar, University of Oulu, Oulu, Finland
    1. "Simulation of HSTL I/O standard based energy efficient frame buffer for digital image processor." In 2014 International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE), pp. 16-20. IEEE, 2014.
  170. Tarandeep Kaur, Chitkara University, Chandigarh, India
  171. Teerath Das, Gran Sasoo Science Institute, Italy
    1. "Simulation of HSTL I/O standard based energy efficient frame buffer for digital image processor." In 2014 International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE), pp. 16-20. IEEE, 2014.
  172. Tukur Gupta, JIIT, Noida, India
  173. Umar Farooq, COMSATS, Lahore, Pakistan
  174. Udita Jindal, Chitkara University, Chandigarh, India
  175. UrmalaRai, Aga Khan Hospital, Karachi, Pakistan
  176. V B Taneja, C-DAC Noida, India
  177. Vaashu Sharma, NIT Hamirpur, India
  178. Vandana Thind, Gyancity Research Lab, India
    1. “SSTL based power efficient implementation of DES security algorithm on 28nm FPGA”, International Journal of Security and its Applications, 9 (7), 2015, pp. 267-274. http://article.nadiapub.com/IJSIA/vol9_no7/23.pdf
    2. "FPGA Based Low Power Router Design Using High Speed Transeceiver Logic IO Standard." Gyancity Journal of Engineering and Technology 1, no. 2 (2015): 24-30.
    3. "FPGA based low power DES algorithm design and implementation using HTML technology." International Journal of Software Engineering and Its Applications 10, no. 6 (2016): 81-92.
    4. “Timing constraints-based high-performance DES design and implementation on 28-nm FPGA”, Advances in Intelligent Systems and Computing, 732, pp. 123-137, 2018. https://link.springer.com/chapter/10.1007/978-981-10-8533-8_13
    5. “Stack Memory Implementation and Analysis of Timing Constraint, Power and Memory using FPGA”, IEEE 9th International Conference on Computational Intelligence and Communication Networks (CICN), 16-17 Sep 2017, Final International University, Cyprus. https://ieeexplore.ieee.org/document/8319388
    6. “Power Analysis of Energy Efficient des Algorithm and Implementation on 28nm FPGA ”, IEEE 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science (DCABES), 24-26 August 2016, Paris, France http://ieeexplore.ieee.org/document/7982309
  179. Vaishali Sharma, Chitkara University, Chandigarh, India
  180. Vaishnavi Bisht, Birla Institute of Applied Sciences, Bhimtal, India
    1. "LVTTL and SSTL IO Standards Based Energy Efficient FSM Design on 16nm Ultrascale Plus FPGA”, 12th International Conference on Computational Intelligence and Communication Networks (CICN), 25-26 September 2020, Bhimtal, India, https://ieeexplore.ieee.org/document/9242605
  181. Veer Pratap Singh, National Institute of Technology, Bhopal
  182. Vidyotma Gandhi, Chitkara University, Chandigarh, India
  183. Vijay Shri Chaurasia, NIT Bhopal, India
  184. Vikas Jha, Gyancity Research Lab, Pune, India
    1. Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA. Advances in Intelligent Systems and Computing, 139–150. doi:10.1007/978-981-10-8533-8_14 https://link.springer.com/chapter/10.1007/978-981-10-8533-8_14
  185. Vikas Verma, IIT Roorkee, India
  186. Viswam Parthiban, National University of Singapore
  187. Waheeb Abu-Ulbeh, UTM, Selangor, Malaysia
    1. “Models of Leadership in Information Technology Projects”, Solid State Technology, Vol. 63, No. 1s, pp. 1534-1542 http://solidstatetechnology.us/index.php/JSST/article/view/3097
    2. "E-Business Possibilities for Homeworker Businesses at Malaysia", International Journal of Innovative Technology and Exploring Engineering, Volume-8 Issue-11S, September 2019, pp. 4869-4874 https://www.ijrte.org/wp-content/uploads/papers/v8i3/C6890098319.pdf
  188. Wanod Kumar, MUET, Pakistan
  189. Yogesh Singh, ABV-IIITM Gwalior, India
  190. Yousef Abubaker Mohamed Ahmed El-Ebiary, Faculty of Informatics and Computing, UniSZA, Malaysia
    1. "Technologies for effective disaster management systems: a state of the art survey of current challenges and opportunities", 3C Tecnología, Special Issue, November 2019 https://www.3ciencias.com/articulos/articulo/technologies-effective-disaster-management-systems/
    2. “FSM Based Green Memory Design and its Implementation on Ultrascale Plus FPGA”, Journal of Critical Reviews, ISSN- 2394-5125, Vol. 7, No. 19, pp.454-458, 2020 http://www.jcreview.com/fulltext/197-1594819368.pdf?1596969111
    3. “Models of Leadership in Information Technology Projects”, Solid State Technology, Vol. 63, No. 1s, pp. 1534-1542 http://solidstatetechnology.us/index.php/JSST/article/view/3097
    4. "The Online Platform Mechanism and Characteristics in Arabic Language Tests for Non-Native Speakers", Test Engineering and Management, VOL 82: JAN/FEB 2020 http://www.testmagzine.biz/index.php/testmagzine/article/view/3419
    5. "The Importance of Rhetorical and the Technological Learning Solutions for Non-Arabic Speakers", Test Engineering and Management, VOL 82: JAN/FEB 2020 http://www.testmagzine.biz/index.php/testmagzine/article/view/3420
    6. "E-Business Possibilities for Homeworker Businesses at Malaysia", International Journal of Innovative Technology and Exploring Engineering, Volume-8 Issue-11S, September 2019, pp. 4869-4874 https://www.ijrte.org/wp-content/uploads/papers/v8i3/C6890098319.pdf
    7. "DIGITIZATION OF THE ARABIC LANGUAGE BETWEEN REALITY AND EXPECTATIONS", International Journal of Recent Technology and Engineering, Volume-8 Issue-2S3, pp. 1151-1158. July 2019 https://www.ijrte.org/wp-content/uploads/papers/v8i2S3/B12130782S319.pdf
    8. "THE IMPACT OF E-LEARNING IN TEACHING ARABIC LANGUAGE FOR NON-NATIVE SPEAKERS",International Journal of Recent Technology and Engineering, Volume-8 Issue-2S3, pp. 1159-1162, July 2019 https://www.ijrte.org/wp-content/uploads/papers/v8i2S3/B12140782S319.pdf
  191. Ytavclerh Vargas, Department of the Faculty of Forestry Research, Universidad Nacional Agraria de la Selva, Tingo Maria, Peru
    1. “Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru Low planting densities for early maturation of Mauritia flexuosa for the sustainable management of plantations in Alto Huallaga, Peru”, World Journal of Engineering ISSN: 1708-5284 https://www.emerald.com/insight/content/doi/10.1108/WJE-09-2020-0416/full/html

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